While merging logic circuits and DRAM arrays on a single chip, one should consider their compatibility in both design and fabrication. FIG. 1 shows cross-section view for part of a single chip having a logic region 30 and an embedded DRAM array region 32. In the DRAM region 32 shown in FIG. 1, metal-insulator-metal (MIM) capacitors 34 are used at each DRAM cell. Each MIM capacitor 34 shown in FIG. 1 includes a top electrode-to-bottom electrode design with a contact-to-top electrode isolation rule.
Decreasing device dimensions continue to create needs for new solutions to DRAM cell array isolation rule limitations. In the prior design shown in FIG. 1, the overlap margin 36 between the top plate electrode contact 38 and the bit line contact 40 may be insufficient in this design as device dimensions shrink. In other words, as device dimensions shrink, it becomes increasingly difficult to provide precise alignment to ensure that the top electrode contact 38 of the MIM capacitor 34 does not overlap with the bit line contact 40. Some minimum margin must exist between the bit line contact 40 and the contact 38 for the top plate electrode 42 for the DRAM device portion 32 to function properly. Hence, a need exist for an improved design to address this overlap margin window to allow for decreased device dimensions in future chips.